The present invention is directed to increasing the memory density of integrated circuit memory chips, more particularly to enabling effective stacking of all types of integrated circuit chips, and more particularly to routing the interface pads of an integrated circuit chip to an edge or sidewall of the chip to enable stacking of the chips and follow-on signal routing.
Over the past decade substantial research and development efforts have been directed towards miniaturizing and increasing the density of integrated circuit (IC) chips or die. There is a current demand, for example, for greater memory density of IC memory chips. One solution to this demand is to package the chips closer together, so that the effective density per unit volume increases. The more efficient packaging of chips to increase the density is to stack them one on top of another into a single three-dimensional (3D) array. In order to stack the chip on top of each other, means must be provided to enable interconnection of the bond or interface pads located on the chip surface, usually the upper or top surface of the chip. Thus, the bond or interface pads must be extended to the edge surfaces or sidewalls of the chip, and must be exposed so that attachment to the next level of packaging is possible.
The present invention provides a means and method for extending the bond or interface pads to one or more edge surfaces or sidewalls of the chip or die. In this invention L-connects or L-shaped interconnects extend from each pad on the surface to a pad formed on an edge surface or side wall of the chip. The interconnects and the sidewall pads are formed by three-dimensional metalization processes, such as laser pantography. Thus, stacking and interconnecting of chips to produce 3D arrays can be readily accomplished.